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8.5.3 Short description

The current approach to producing transistor chips employs photolithography. The basic process involves applying a photoresist material to a substrate wafer (possibly by spin coating). Light is then applied to the wafer through a mask, which renders soluble the photoresist material upon which the light falls. A developer solution is then used to remove the soluble photoresist. The material that is not protected by the remaining photoresist is etched away. Finally the photoresist material is also removed. The light source used is currently deep ultraviolet.

A limit which now comes into play is that lithography techniques are limited in how small they can scale by the wavelength of the light source used. This has been addressed with several approaches which scale existing technology and which, whilst perhaps not being classical nanotechnology, are still worth describing here.
These approaches obtain smaller feature sizes by adjusting three parameters of the manufacturing process; scaling the wavelength of the light source uses (as in EUVL), increasing the refractive index of the immersion medium, or increasing the k1 factor (a term which covers several of the error sources in the lithography process).

1. Immersion Lithography

Immersion Lithography employs a liquid between lens and wafer which has a refractive index greater than one. This enables scaling down the wavelength of the light source. The immersion medium that is typically used is highly purified water, which creates feature sizes of 37nm. Immersion lithography is seeing industrial adoption.

2. Extreme Ultraviolet Lithography

Extreme Ultraviolet Lithography (EUVL) uses mirrors to focus the UV beam, enabling the creation of sub- 100nm feature sizes. The EUVL wavelength is 13.5nm. The process occurs in a vacuum, so that air molecules do not distort the EUVL beam, and requires highly reflective optics so that the beam is not distorted nor stripped of power.
One of the new features of the EUVL is the increased energy of the EUVL photons, which leads to roughness of the feature sizes. Groups at CNSE in New York and at IMEC in Belgium are developing test chips with EUVL, reporting feature sizes of 60-90nm.

Challenges in the development process of EUVL, have set back the introduction of this technology. The most pressing obstacle is the identification of reliable high power sources, followed by the challenge of producing defect free masks. Identifying suitable resist materials, which was a major obstacle, has shown progress recently. The suggestion is that EUVL will not be introduced until 2012 at the earliest, at the 16nm node.

3. Computational Methods

The third approach to scaling existing lithography processes is to use computational methods to optimise? adapt 193nm wavelength light sources to create 32nm and even 22nm feature sizes.
Process elements that can be optimised include the layout of the masks and the intensity of illumination at different points. One example is to reduce the intensity of the light source at points where multiple detailed features are close together, to avoid roughness in the patterning of the substrate.

This type of process modelling has highly intensive computing requirements, given the number of factors that must be analysed.